by disk91 Sat May 21, 2016 9:59 am
compilation is working well but download is a problem.
any advice with jlink or cflash ?
here is what i get with jlink :
J-Link>connect
Device "EFM32G210F128" selected.
Found SWD-DP with ID 0x2BA01477
Found Cortex-M3 r2p0, Little endian.
FPUnit: 0 code (BP) slots and 0 literal slots
CoreSight components:
ROMTbl 0 @ E00FF000
ROMTbl 0 [1]: FFF0F000, CID: FFF03D03, PID: 2BB00005 ???
ROMTbl 0 [2]: FFF02000, CID: 05E00D2B, PID: 2BB00205 ???
ROMTbl 0 [3]: FFF03000, CID: 05E00D2B, PID: 2BB00305 ???
ROMTbl 0 [4]: 00000000, CID: 05100D00, PID: 0F300105 ???
ROMTbl 0 [5]: FFF41000, CID: 05900D0F, PID: 2BB92305 ???
Cortex-M3 identified.
J-Link>r
Reset delay: 0 ms
Reset type NORMAL: Resets core & peripherals via SYSRESETREQ & VECTRESET bit.
**************************
WARNING: Could not set S_RESET_ST
**************************
**************************
WARNING: CPU did not halt after reset.
**************************
**************************
WARNING: T-bit of XPSR is 0 but should be 1. Changed to 1.
**************************
**************************
WARNING: S_RESET_ST not cleared
**************************
Found SWD-DP with ID 0x2BA01477
Found Cortex-M3 r2p0, Little endian.
SYSRESETREQ has confused core. Trying to reconnect and use VECTRESET.
Found SWD-DP with ID 0x2BA01477
Found Cortex-M3 r2p0, Little endian.
**************************
WARNING: Failed to reset CPU. VECTRESET has confused core.
**************************
**************************
WARNING: CPU did not halt after reset.
**************************
**************************
WARNING: T-bit of XPSR is 0 but should be 1. Changed to 1.
**************************
**************************
WARNING: S_RESET_ST not cleared
**************************
Paul